Goossens, Bernard Guide to Computer Processor Architecture 9783031180224

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Автор: Goossens, Bernard
Название: Guide to Computer Processor Architecture
ISBN: 9783031180224
Издательство: Springer
Классификация:

Аппаратное обеспечение коипьютеров

Операционные системы

Технология разработки программного обеспечения

Архитектура и логическое построение вычислительных систем

ISBN-10: 3031180224
Обложка/Формат: Paperback
Страницы: 439
Вес: 0.87 кг.
Дата издания: 15.01.2023
Серия: Undergraduate topics in computer science
Язык: English
Издание: 1st ed. 2023
Иллюстрации: 196 illustrations, color; 65 illustrations, black and white; xxv, 439 p. 261 illus., 196 illus. in color.
Размер: 156 x 234 x 27
Читательская аудитория: Professional & vocational
Подзаголовок: A risc-v approach, with high-level synthesis
Ссылка на Издательство: Link
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Поставляется из: Германии
Описание: This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Universit? de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.
Дополнительное описание: Part I. Single core processors.- 1. Getting Ready.- 2. Building a RISC-V Processor.- 3. Building a Pipelined RISC-V Processor.- 4. Building a RISC-V Processor with a Multi-cycle Pipeline.- 5. Building a RISC-V Processor with a Multiple Hart Pipeline.- Par

Guide to Computer Processor Architecture, Goossens, Bernard