VLSI Physical Design: From Graph Partitioning to Timing Closure, Kahng
Автор: Andrew B. Kahng; Jens Lienig; Igor L. Markov; Jin Название: VLSI Physical Design: From Graph Partitioning to Timing Closure ISBN: 9400790201 ISBN-13(EAN): 9789400790209 Издательство: Springer Рейтинг: Цена: 65210.00 T Наличие на складе: Есть у поставщика Поставка под заказ. Описание: LSI Physical Design explores how algorthims can be used to create a geometric chip layout can be created from an abstract circuit design. The text emphasizes essential, fundamental techniques, ranging from hypergraph partictioning and circuit placement to timing closure.
Автор: Gangadharan Название: Constraining Designs for Synthesis and Timing Analysis ISBN: 1461432685 ISBN-13(EAN): 9781461432685 Издательство: Springer Рейтинг: Цена: 111790.00 T Наличие на складе: Есть у поставщика Поставка под заказ. Описание: This guide to timing constraints in integrated circuit design shows how to maximize performance of IC designs by specifying timing requirements correctly. Coverage includes such design aspects as synthesis, static timing analysis and placement and routing.
Автор: David E. Hudak; Santosh G. Abraham Название: Compiling Parallel Loops for High Performance Computers ISBN: 0792392833 ISBN-13(EAN): 9780792392835 Издательство: Springer Рейтинг: Цена: 135050.00 T Наличие на складе: Есть у поставщика Поставка под заказ. Описание: The exploitation of parallel processing to improve computing speeds is being examined at various levels of computer science. This book evaluates these tradeoffs to generate optimum cyclic partitions for data-parallel loops with a linearly varying or uniform computational structure and neighborhood or dimensional multicast communication patterns.
Автор: Vikram Iyengar; Anshuman Chandra Название: Test Resource Partitioning for System-on-a-Chip ISBN: 1461354005 ISBN-13(EAN): 9781461354000 Издательство: Springer Рейтинг: Цена: 93160.00 T Наличие на складе: Есть у поставщика Поставка под заказ.
Автор: David E. Hudak; Santosh G. Abraham Название: Compiling Parallel Loops for High Performance Computers ISBN: 1461363861 ISBN-13(EAN): 9781461363866 Издательство: Springer Рейтинг: Цена: 93160.00 T Наличие на складе: Есть у поставщика Поставка под заказ. Описание: 2 Code Segments . . . . . . . . . . . . . . . 3 Determining Communication Parameters . 5 Partitioning . . . . . . 6 Experimental Results . . . . . . . . . . . . . . . . 3 The CPR Algorithm . . . . 149 INDEX . . . . . . . . . . . . . . . . . 2 Example of an iterative data-parallel loop . . . . . . . . . . . . . . . . . .
Название: Routing Placement And Partitioning ISBN: 0893917842 ISBN-13(EAN): 9780893917845 Издательство: Elsevier Science Рейтинг: Цена: 70250.00 T Наличие на складе: Невозможна поставка. Описание: With rapid advances in VLSI technology, the routing problem has come to assume a position of significance and is one of the most widely investigated problems in VLSI design automation. Specific elements included in the discussion are the library cell approach and slicing topology.
Автор: Golshan Khosrow Название: The Art of Timing Closure: Advanced ASIC Design Implementation ISBN: 303049635X ISBN-13(EAN): 9783030496357 Издательство: Springer Рейтинг: Цена: 74530.00 T Наличие на складе: Есть у поставщика Поставка под заказ. Описание:
Chapter 1. Introduction.- Chapter 2. Design Implementation Data Structures and Settings.- Chapter 3. Design Constraints Development.- Chapter 4. Multiple Modes and Multiple Corners Development.- Chapter 5. Concurrent Floor Planning and Placement.- Chapter 6. Placement and Timing Analysis.- Chapter 7. Clock Tree Synthesis and Timing Analysis.- Chapter 8. Detail Route and Timing, Power Analysis.- Chapter 9. Final Route and Timing Closure in all Modes and Corners.- Chapter 10. Functional and Physical Verification.
The Art of Timing Closure is written using a hands-on approach to describe advanced concepts and techniques using Multi-Mode Multi-Corner (MMMC) for an advanced ASIC design implementation. It focuses on the physical design, Static Timing Analysis (STA), formal and physical verification.
The scripts in this book are based on Cadence(R) Encounter System(TM). However, if the reader uses a different EDA tool, that tool's commands are similar to those shown in this book.
The topics covered are as follows:
Data Structures
Multi-Mode Multi-Corner Analysis
Design Constraints
Floorplan and Timing
Placement and Timing
Clock Tree Synthesis
Final Route and Timing
Design Signoff
Rather than go into great technical depth, the author emphasizes short, clear descriptions which are implemented by references to authoritative manuscripts. It is the goal of this book to capture the essence of physical design and timing analysis at each stage of the physical design, and to show the reader that physical design and timing analysis engineering should be viewed as a single area of expertise.
This book is intended for anyone who is involved in ASIC design implementation -- starting from physical design to final design signoff. Target audiences for this book are practicing ASIC design implementation engineers and students undertaking advanced courses in ASIC design.
Автор: Vasant B. Rao; David V. Overhauser; Timothy N. Tri Название: Switch-Level Timing Simulation of MOS VLSI Circuits ISBN: 1461289637 ISBN-13(EAN): 9781461289630 Издательство: Springer Рейтинг: Цена: 153720.00 T Наличие на складе: Есть у поставщика Поставка под заказ. Описание: Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging.
Автор: Ashish Srivastava; Dennis Sylvester; David Blaauw Название: Statistical Analysis and Optimization for VLSI: Timing and Power ISBN: 1441938273 ISBN-13(EAN): 9781441938275 Издательство: Springer Рейтинг: Цена: 130590.00 T Наличие на складе: Есть у поставщика Поставка под заказ. Описание: Comprises a valuable reference for statistical analysis and optimization techniques in current and future VLSI design for CAD-Tool developers and for researchers interested in starting work in this very active area of research.
Автор: Vasant B. Rao; David V. Overhauser; Timothy N. Tri Название: Switch-Level Timing Simulation of MOS VLSI Circuits ISBN: 0898383021 ISBN-13(EAN): 9780898383027 Издательство: Springer Рейтинг: Цена: 158380.00 T Наличие на складе: Есть у поставщика Поставка под заказ. Описание: Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging.
Автор: Naresh Maheshwari; S. Sapatnekar Название: Timing Analysis and Optimization of Sequential Circuits ISBN: 1461375797 ISBN-13(EAN): 9781461375791 Издательство: Springer Рейтинг: Цена: 93160.00 T Наличие на складе: Есть у поставщика Поставка под заказ.
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