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VLSI Physical Design: From Graph Partitioning to Timing Closure, Kahng


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Автор: Kahng
Название:  VLSI Physical Design: From Graph Partitioning to Timing Closure
ISBN: 9783030964146
Издательство: Springer
Классификация:


ISBN-10: 3030964140
Обложка/Формат: Hardback
Страницы: 317
Вес: 0.67 кг.
Дата издания: 30.06.2022
Язык: English
Издание: 2nd ed. 2022
Иллюстрации: 335 illustrations, black and white; xvii, 325 p. 335 illus.
Размер: 242 x 161 x 26
Читательская аудитория: Professional & vocational
Основная тема: Engineering
Ссылка на Издательство: Link
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Поставляется из: Германии
Описание: The complexity of modern chip design requires extensive use of specialized software throughout the process. To achieve the best results, a user of this software needs a high-level understanding of the underlying mathematical models and algorithms. In addition, a developer of such software must have a keen understanding of relevant computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. This book introduces and compares the fundamental algorithms that are used during the IC physical design phase, wherein a geometric chip layout is produced starting from an abstract circuit design. This updated second edition includes recent advancements in the state-of-the-art of physical design, and builds upon foundational coverage of essential and fundamental techniques. Numerous examples and tasks with solutions increase the clarity of presentation and facilitate deeper understanding. A comprehensive set of slides is available on the Internet for each chapter, simplifying use of the book in instructional settings. “This improved, second edition of the book will continue to serve the EDA and design community well. It is a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools and design the most advanced micro-electronics.” Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Systems Group “This is the book I wish I had when I taught EDA in the past, and the one I’m using from now on.” Dr. Louis K. Scheffer, Howard Hughes Medical Institute “I would happily use this book when teaching Physical Design. I know of no other work that’s as comprehensive and up-to-date, with algorithmic focus and clear pseudocode for the key algorithms. The book is beautifully designed!” Prof. John P. Hayes, University of Michigan “The entire field of electronic design automation owes the authors a great debt for providing a single coherent source on physical design that is clear and tutorial in nature, while providing details on key state-of-the-art topics such as timing closure.” Prof. Kurt Keutzer, University of California, Berkeley “An excellent balance of the basics and more advanced concepts, presented by top experts in the field.” Prof. Sachin Sapatnekar, University of Minnesota
Дополнительное описание: 1 Introduction.- 2 Netlist and System Partitioning.- 3 Chip Planning.- 4 Global and Detailed Placement.- 5 Global Routing.- 6 Detailed Routing.- 7 Specialized Routing.- 8 Timing Closure. A Solutions to Chapter Exercises.- B Example CMOS Cell Layouts.


VLSI Physical Design: From Graph Partitioning to Timing Closure

Автор: Andrew B. Kahng; Jens Lienig; Igor L. Markov; Jin
Название: VLSI Physical Design: From Graph Partitioning to Timing Closure
ISBN: 9400790201 ISBN-13(EAN): 9789400790209
Издательство: Springer
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Цена: 65210.00 T
Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: LSI Physical Design explores how algorthims can be used to create a geometric chip layout can be created from an abstract circuit design. The text emphasizes essential, fundamental techniques, ranging from hypergraph partictioning and circuit placement to timing closure.

Constraining Designs for Synthesis and Timing Analysis

Автор: Gangadharan
Название: Constraining Designs for Synthesis and Timing Analysis
ISBN: 1461432685 ISBN-13(EAN): 9781461432685
Издательство: Springer
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Цена: 111790.00 T
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Описание: This guide to timing constraints in integrated circuit design shows how to maximize performance of IC designs by specifying timing requirements correctly. Coverage includes such design aspects as synthesis, static timing analysis and placement and routing.

Compiling Parallel Loops for High Performance Computers

Автор: David E. Hudak; Santosh G. Abraham
Название: Compiling Parallel Loops for High Performance Computers
ISBN: 0792392833 ISBN-13(EAN): 9780792392835
Издательство: Springer
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Цена: 135050.00 T
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Описание: The exploitation of parallel processing to improve computing speeds is being examined at various levels of computer science. This book evaluates these tradeoffs to generate optimum cyclic partitions for data-parallel loops with a linearly varying or uniform computational structure and neighborhood or dimensional multicast communication patterns.

Test Resource Partitioning for System-on-a-Chip

Автор: Vikram Iyengar; Anshuman Chandra
Название: Test Resource Partitioning for System-on-a-Chip
ISBN: 1461354005 ISBN-13(EAN): 9781461354000
Издательство: Springer
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Цена: 93160.00 T
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Compiling Parallel Loops for High Performance Computers

Автор: David E. Hudak; Santosh G. Abraham
Название: Compiling Parallel Loops for High Performance Computers
ISBN: 1461363861 ISBN-13(EAN): 9781461363866
Издательство: Springer
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Цена: 93160.00 T
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Описание: 2 Code Segments . . . . . . . . . . . . . . . 3 Determining Communication Parameters . 5 Partitioning . . . . . . 6 Experimental Results . . . . . . . . . . . . . . . . 3 The CPR Algorithm . . . . 149 INDEX . . . . . . . . . . . . . . . . . 2 Example of an iterative data-parallel loop . . . . . . . . . . . . . . . . . .

Название: Routing Placement And Partitioning
ISBN: 0893917842 ISBN-13(EAN): 9780893917845
Издательство: Elsevier Science
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Цена: 70250.00 T
Наличие на складе: Невозможна поставка.
Описание: With rapid advances in VLSI technology, the routing problem has come to assume a position of significance and is one of the most widely investigated problems in VLSI design automation. Specific elements included in the discussion are the library cell approach and slicing topology.

The Art of Timing Closure: Advanced ASIC Design Implementation

Автор: Golshan Khosrow
Название: The Art of Timing Closure: Advanced ASIC Design Implementation
ISBN: 303049635X ISBN-13(EAN): 9783030496357
Издательство: Springer
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Цена: 74530.00 T
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Описание:

Chapter 1. Introduction.- Chapter 2. Design Implementation Data Structures and Settings.- Chapter 3. Design Constraints Development.- Chapter 4. Multiple Modes and Multiple Corners Development.- Chapter 5. Concurrent Floor Planning and Placement.- Chapter 6. Placement and Timing Analysis.- Chapter 7. Clock Tree Synthesis and Timing Analysis.- Chapter 8. Detail Route and Timing, Power Analysis.- Chapter 9. Final Route and Timing Closure in all Modes and Corners.- Chapter 10. Functional and Physical Verification.


The Art of Timing Closure: Advanced ASIC Design Implementation

Автор: Golshan Khosrow
Название: The Art of Timing Closure: Advanced ASIC Design Implementation
ISBN: 3030496384 ISBN-13(EAN): 9783030496388
Издательство: Springer
Цена: 74530.00 T
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Описание:

The Art of Timing Closure is written using a hands-on approach to describe advanced concepts and techniques using Multi-Mode Multi-Corner (MMMC) for an advanced ASIC design implementation. It focuses on the physical design, Static Timing Analysis (STA), formal and physical verification.

The scripts in this book are based on Cadence(R) Encounter System(TM). However, if the reader uses a different EDA tool, that tool's commands are similar to those shown in this book.

The topics covered are as follows:

  • Data Structures
  • Multi-Mode Multi-Corner Analysis
  • Design Constraints
  • Floorplan and Timing
  • Placement and Timing
  • Clock Tree Synthesis
  • Final Route and Timing
  • Design Signoff

Rather than go into great technical depth, the author emphasizes short, clear descriptions which are implemented by references to authoritative manuscripts. It is the goal of this book to capture the essence of physical design and timing analysis at each stage of the physical design, and to show the reader that physical design and timing analysis engineering should be viewed as a single area of expertise.

This book is intended for anyone who is involved in ASIC design implementation -- starting from physical design to final design signoff. Target audiences for this book are practicing ASIC design implementation engineers and students undertaking advanced courses in ASIC design.


Switch-Level Timing Simulation of MOS VLSI Circuits

Автор: Vasant B. Rao; David V. Overhauser; Timothy N. Tri
Название: Switch-Level Timing Simulation of MOS VLSI Circuits
ISBN: 1461289637 ISBN-13(EAN): 9781461289630
Издательство: Springer
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Цена: 153720.00 T
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Описание: Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging.

Statistical Analysis and Optimization for VLSI:  Timing and Power

Автор: Ashish Srivastava; Dennis Sylvester; David Blaauw
Название: Statistical Analysis and Optimization for VLSI: Timing and Power
ISBN: 1441938273 ISBN-13(EAN): 9781441938275
Издательство: Springer
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Цена: 130590.00 T
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Описание: Comprises a valuable reference for statistical analysis and optimization techniques in current and future VLSI design for CAD-Tool developers and for researchers interested in starting work in this very active area of research.

Switch-Level Timing Simulation of MOS VLSI Circuits

Автор: Vasant B. Rao; David V. Overhauser; Timothy N. Tri
Название: Switch-Level Timing Simulation of MOS VLSI Circuits
ISBN: 0898383021 ISBN-13(EAN): 9780898383027
Издательство: Springer
Рейтинг:
Цена: 158380.00 T
Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging.

Timing Analysis and Optimization of Sequential Circuits

Автор: Naresh Maheshwari; S. Sapatnekar
Название: Timing Analysis and Optimization of Sequential Circuits
ISBN: 1461375797 ISBN-13(EAN): 9781461375791
Издательство: Springer
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Цена: 93160.00 T
Наличие на складе: Есть у поставщика Поставка под заказ.


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