Buccella Pietro, Stefanucci Camillo, Kayal Maher Parasitic Substrate Coupling in High Voltage Integrated Circuits: Minority and Majority Carriers Propagation in Semiconductor Substrate 9783030089764

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Автор: Buccella Pietro, Stefanucci Camillo, Kayal Maher
Название: Parasitic Substrate Coupling in High Voltage Integrated Circuits: Minority and Majority Carriers Propagation in Semiconductor Substrate
ISBN: 9783030089764
Издательство: Springer
Классификация:

Устойчивое развитие

Электроника

Схемы и компоненты

ISBN-10: 3030089762
Обложка/Формат: Paperback
Страницы: 204
Вес: 0.29 кг.
Дата издания: 05.04.2019
Серия: Analog circuits and signal processing
Язык: English
Издание: Softcover reprint of
Иллюстрации: 76 tables, color; 73 illustrations, color; 51 illustrations, black and white; xvii, 183 p. 124 illus., 73 illus. in color.
Размер: 234 x 156 x 11
Читательская аудитория: General (us: trade)
Подзаголовок: Minority and majority carriers propagation in semiconductor substrate
Ссылка на Издательство: Link
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Поставляется из: Германии
Описание: This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.

Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;
Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;
Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;
Offers design guidelines to reduce couplings by adding specific protections.
Дополнительное описание: Chapter1: Overview of Parasitic Substrate Coupling.- Chapter2: Design Challenges in High Voltage ICs.- Chapter3: Substrate Modeling with Parasitic Transistors.- Chapter4: TCAD Validation of the Model.- Chapter5: Extraction Tool for the Substrate Network.-

Parasitic Substrate Coupling in High Voltage Integrated Circuits: Minority and Majority Carriers Propagation in Semiconductor Substrate, Buccella Pietro, Stefanucci Camillo, Kayal Maher