Debashis Bhattacharya; John P. Hayes Hierarchical Modeling for VLSI Circuit Testing 9781461288190

Варианты приобретения

Цена: 121070.00T
Кол-во:
Наличие: Поставка под заказ. Есть в наличии на складе поставщика.
Склад Америка: 225 шт.
При оформлении заказа до: 2025-07-28
Ориентировочная дата поставки: Август-начало Сентября
При условии наличия книги у поставщика.

Добавить в корзину

в Мои желания

Автор: Debashis Bhattacharya; John P. Hayes
Название: Hierarchical Modeling for VLSI Circuit Testing
ISBN: 9781461288190
Издательство: Springer
Классификация: ISBN-10: 1461288193
Обложка/Формат: Paperback
Страницы: 160
Вес: 0.25 кг.
Дата издания: 26.09.2011
Серия: The Springer International Series in Engineering and Computer Science
Язык: English
Размер: 234 x 156 x 10
Основная тема: Computer Science
Ссылка на Издательство: Link
Рейтинг:
Поставляется из: Германии
Описание: Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob- lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

Hierarchical Modeling for VLSI Circuit Testing, Debashis Bhattacharya; John P. Hayes