Universal Verification Methodology Based Verification Environment 9783659476044

Варианты приобретения

Цена: 36760.00T
Кол-во:
Наличие: Поставка под заказ. Есть в наличии на складе поставщика.
Склад Америка: 216 шт.
При оформлении заказа до:
Ориентировочная дата поставки:
При условии наличия книги у поставщика.

Добавить в корзину

в Мои желания

Автор: Abhishek Jain
Название: Universal Verification Methodology Based Verification Environment
ISBN: 9783659476044
Издательство: LAP LAMBERT Academic Publishing
Классификация:

Информационные технологии: общие вопросы

ISBN-10: 3659476048
Обложка/Формат: Paperback
Страницы: 140
Вес: 0.21 кг.
Дата издания: 19.01.2014
Серия: transaction level modeling, SystemVerilog, Universal Verification Methodology (UVM), Register interface, Universal Verification Component (UVC), Register and memory model, IP-XACT, Virtual Register Interface (VRI), Reference model, Assertion Based VI
Язык: English
Иллюстрации: Black & white illustrations
Размер: 229 x 152 x 8
Читательская аудитория: General (us: trade)
Рейтинг:
Описание: Ever increasing silicon design complexity and transistor density, product differentiation and time to market are major factors creating huge pressure on complete design flow. This book covers Verification phase by describing the concepts of Universal Verification Methodology (UVM) and by presenting a pragmatic approach of developing efficient and unified advanced verification environment at all levels using Universal Verification Methodology along with Assertion based verification, hardware acceleration and Transaction Level Modeling. This book is written primarily for verification engineers performing verification of complex IP blocks or entire system-on-chip (SoC) designs. However, much of material will also be of interest to SoC project managers as well as designers to learn more about verification. Furthermore, this book includes detailed information about verification environment for one case which can be easily used as reference for other cases.

Universal Verification Methodology Based Verification Environment, Abhishek Jain