Digital Integrated Circuit Design Using Verilog and SystemVerilog, Ronald W. Mehler

Автор: T. R. Padmanabhan
Название: Design Through Verilog HDL
ISBN: 0471441481 ISBN-13(EAN): 9780471441489
Издательство: Wiley
Рейтинг:
Цена: 98270.00 T
Наличие на складе: Есть
Описание: Verilog provides platforms for designs to be described at different layers of complexity, combine them in a seamless manner, test them at every stage and build up a bug-free design. This book intends to guide readers to master Verilog as an HDL and use it for design.

Автор: Bergeron
Название: Writing Testbenches using SystemVerilog
ISBN: 0387292217 ISBN-13(EAN): 9780387292212
Издательство: Springer
Рейтинг:
Цена: 186330.00 T
Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology.Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model.Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.

Автор: Vijayaraghavan Srikanth, Ramanathan Meyyappan
Название: A Practical Guide for SystemVerilog Assertions
ISBN: 0387260498 ISBN-13(EAN): 9780387260495
Издательство: Springer
Рейтинг:
Цена: 174150.00 T
Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: SystemVerilog language consists of three very specific areas of constructs -- design, assertions and testbench.  Assertions add a whole new dimension to the ASIC verification process.  Assertions provide a better way to do verification proactively.  Traditionally, engineers are used to writing verilog test benches that help simulate their design.  Verilog is a procedural language and is very limited in capabilities to handle the complex Asic's built today.  SystemVerilog assertions (SVA) are a declarative and temporal language that provides excellent control over time and parallelism.  This provides the designers a very strong tool to solve their verification problems.  While the language is built solid, the thinking is very different from the user's perspective when compared to standard verilog language.  The concept is still very new and there is not enough expertise in the field to adopt this methodology and be successful.  While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems.  This book will be the practical guide that will help people to understand this new methodology."Today's SoC complexity coupled with time-to-market and first-silicon success pressures make assertion based verification a requirement and this book points the way to effective use of assertions."Satish S. Iyengar, Director, ASIC Engineering, Crimson Microsystems, Inc."This book benefits both the beginner and the more advanced users of SystemVerilog Assertions (SVA).  First by introducing the concept of Assertion Based Verification (ABV) in a simple to understand way, then by discussing the myriad of ideas in a broader scope that SVA can accommodate.  The many real life examples, provided throughout the book, are especially useful."Irwan Sie, Director, IC Design, ESS Technology, Inc."SystemVerilog Assertions is a new language that can find and isolate bugs early in the design cycle.  This book shows how to verify complex protocols and memories using SVA with seeral examples.  This book is a good reference guide for both design and verification engineers."Derick Lin, Senior Director, Engineering, Airgo Networks, Inc.

Автор: Vahid Frank
Название: Digital Design with RTL Design, Verilog and VHDL
ISBN: 0470531088 ISBN-13(EAN): 9780470531082
Издательство: Wiley
Рейтинг:
Цена: 255540.00 T
Наличие на складе: Поставка под заказ.
Описание: Unique with its RTL-early organization, Vahid`s text supports instructors wishing to develop strong design skills in their students. The emergence of parallel processing, multicore processors and FPGAs are blurring the lines between hardware and software and fundamentally altering the way digital design and design logic should be taught.

Автор: Lilja
Название: Designing Digital Computer Systems with Verilog
ISBN: 052182866X ISBN-13(EAN): 9780521828666
Издательство: Cambridge Academ
Рейтинг:
Цена: 53850.00 T
Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: This is both an introduction to computer architecture and a guide to using a hardware description language (HDL) to design a simple processor. The authors demonstrate how behavioural and structural models can be developed using the popular Verilog HDL. For senior and graduate students, and practising engineers.